A heterostructure field-effect transistor (FET) is a transistor having an interface (heterointerface) consisting of two materials with different properties such as lattice constants, and two-dimensional electron gas formed at the heterointerface is made a channel. As a heterostructure FET, GaN-based FET is known. As the GaN-based FET, AlGaN/GaN heterostructure FET is known (see for example, following patent document 1 (Japanese Patent application laid-open No. 2003-258005), patent document 2 (Japanese patent application laid-open No. 2003-243424)). This AlGaN/GaN heterostructure FET can obtain a high two-dimensional electron density due to a polarization effect. FIG. 8 shows a schematic diagram of a general heterostructure FET. As shown in FIG. 8, the heterostructure FET includes a substrate 2, a buffer layer 3 provided on the substrate, a channel layer 4 provided on the buffer layer, a spacer layer 5 provided on the channel layer, and a barrier layer 6 provided on the spacer layer. Generally, a source electrode 7, a gate electrode 8, and a drain electrode 9 are provided.
In order to increase gate effectiveness of the transistor and to improve transconductance (gm), it is desirable to reduce the thickness of the AlGaN barrier layer. However, when the thickness of the AlGaN layer is reduced, the effect of the electric field due to the AlGaN surface states at the AlGaN/GaN heterointerface is increased. This brings problems that the polarization effect at the heterointerface is reduced, the two-dimensional electron density is reduced, and the resistance of the channel is increased.
Therefore, in order to improve the performance of the AlGaN/GaN heterostructure transistor, and to respond to increase in speed and frequency, it is effective to reduce the thickness of the AlGaN layer, while simultaneously reducing the effect of the electric field due to the AlGaN surface states, in order to increase the polarization effect at the AlGaN/GaN heterointerface and increase the two-dimensional electron density. From this view point, a recessed-gate FET is known, in which a cap layer and the barrier layer just under the gate electrode portion are dug down by etching to make the gate electrode closer to the channel layer (for example, the following non-patent document 1 (Yoshiaki SANO, Katsuaki KAIFU, Juro MITA and Takashi EGAWA, “Recessed gate nitride field effect transistor with high transconductance characteristics”, Oyo Buturi, Vol. 73, No. 3 Pages 358-362, 2004), and patent document 3 (Japanese patent application laid-open No. 2004-186679). As shown in FIG. 1 of the non-patent document 1 and FIG. 3 of the patent document 3, in the recessed-gate FET, a portion under the gate electrode in the barrier layer and the cap layer is deeply etched.
By using such a recessed-gate FET, it is said that the gate effectiveness of the transistor can be increased almost without reducing outputs of the electric current and electric power, and that this recessed gate structure is formed by reactive ion etching and the like using BCl3 gas and the like. However, since a gas ion etching is required in order to produce a recessed-gate FET, the process becomes complicated. Also, since gas activated by plasma is used for etching, the etched semiconductor surface is damaged. Also, since the reactive ion etching is not very accurate, it is difficult in reality to obtain appropriate recessed-gate FETs with a good reproducibility.